Abstrak
The research and development in modeling and simulation of human cognizance functions requires a high performance computing platform for large-scale mathematical models. Traditional computing architecture cannot fulfill the needs in arithmetic computation and communication bandwidth. This work presents a hybrid computing architecture that consists of a general purpose microprocessor and a hardware accelerator for accelerating the BSB model operations, recall and training. The BSB model, an associative neural network was first described by Anderson et al. (1977) is used primarily to model the effects of human cognizance functions. This work proposes an architecture and FPGA (Field Programmable Gate Array) design for 128-neuron BSB model, for both recall and training operations. This work also proposes a design for implementing multiple 128-neuron BSB models on a single FPGA and the design was tested by performing a demo on a host PC. The pattern recognition application was extensively tested on the 128-neuron BSB model. Experimental results show that, hardware implementation of 128-neuron BSB model is 7.4x faster than the software only implementation.